The present invention pertains to the technical field of signal hold circuits. In particular, the present invention pertains to a peak hold circuit that outputs the signal of a waveform that varies to follow the peak value of a prescribed signal.
The Read-channel circuit of an MOD (Magnetic optical disk) has a peak hold circuit that outputs the peak value of an analog signal that increases and decreases periodically.
As shown in FIG. 4, a conventional peak hold circuit 101 has comparator 111, current output circuit 112 and capacitor 113.
The inverting input terminal (xe2x88x92) of comparator (111) is connected to input terminal (114). The comparator outputs a comparison signal, to be described later, corresponding to the analog voltage DI input to input terminal (114).
Current output circuit (112) has switch transistor (121), diode (122), source-side constant current circuit (123), and sink-side constant current circuit (124).
The output terminal of comparator (111) is connected to the gate terminal of switch transistor (121). Switch transistor (121) is turned on or off corresponding to the comparison signal output from comparator (111). Source-side constant current circuit (123) is connected to the terminal of capacitor (113) on the high potential side via switch transistor (121) and diode (122). When switch transistor (121) is turned on, a source-side constant current I1 is supplied to capacitor (113).
Sink-side constant current circuit (124) is directly connected to the terminal of capacitor (113) on the high potential side, while the terminal of capacitor (113) on the low potential side is grounded. Sink-side constant current circuit (124) always absorbs sink constant current I2 from capacitor (113).
As a result, when switch transistor (121) is turned on, capacitor (113) is charged by constant current (I1xe2x88x92I2) as the difference between source constant current I1 and sink constant current I2, and the voltage across capacitor (113) rises. On the other hand, when switch transistor (121) is turned off, source-side constant current circuit (123) is cut off from capacitor (113), and capacitor (113) is discharged as sink constant current I2 from capacitor (113) is sunk. As a result, the voltage across capacitor (113) drops.
The terminal of capacitor (113) on the high potential side is connected to output terminal (115). The voltage across capacitor (113) is output, from output terminal (115) as output signal Vout, to an external circuit not shown in the figure.
Output terminal (115) is connected to the non-inverting input terminal (+) of comparator (111). The aforementioned analog voltage DI and output signal Vout are input to comparator (111). Comparator (111) compares output signal Vout with analog voltage DI, generates a comparison signal according to the comparison, and outputs the comparison signal to the gate terminal of switch transistor (121). The comparison signal is a low-level signal if output signal Vout is lower than analog voltage DI, and becomes a high-level signal if the output signal is higher than the analog voltage.
Switch transistor (121) is a P-channel MOS transistor. It will be turned on when the comparison signal is low level, and will be turned off when the comparison signal is high level. As described above, output signal Vout varies such that it drops when output signal Vout is higher but rises when it is lower than analog voltage DI. The amount of rise in output voltage Vout per unit time is determined by constant current (I1xe2x88x92I2), that is, the difference between source constant current I1 and sink constant current I2. The amount of drop per unit time is determined by sink constant current I2.
Analog voltage DI is an AC signal with a prescribed frequency, such as a voice signal. The relationship between analog voltage DI and output signal Vout will be explained with reference to FIG. 5. With time plotted on the abscissa and voltage on the ordinate, the waveforms of said analog voltage DI and output signal Vout are shown as curves (W) and (X) in FIG. 5, respectively.
When output signal Vout is lower than analog voltage DI and analog voltage DI rises, output signal Vout rises. When analog voltage DI rises and output signal Vout is lower than analog voltage DI at the time when the analog voltage reaches the peak value (symbol tp in the figure), analog voltage DI drops after time tp when it reaches the peak value. On the other hand, output signal Vout rises. After that, the magnitude relationship between output signal Vout and analog voltage DI is reversed. The reversal time is indicated by tb in FIG. 5.
After time tb when the magnitude relationship between output signal Vout and analog voltage DI is reversed, output signal Vout becomes higher than analog voltage DI. Capacitor (113) is discharged as sink constant current I2 from capacitor (113) is sunk. As a result, output signal Vout starts to drop. The amount of drop of output signal Vout per unit time is determined by the aforementioned sink constant current I2. However, output signal Vout drops more gradually than does analog voltage DI because the sink current I2 is preset to a small value.
During the period when output signal Vout drops, the AC analog voltage DI first drops and then rises until reaching the peak value. However, depending on the magnitude of the peak value of analog voltage DI, the trace of the voltage value of output signal Vout and the trace of the voltage value of analog voltage DI will or will not cross before analog voltage DI rises to the peak value.
If analog voltage DI has a large peak value and the trace of the voltage value of output signal Vout crosses the trace of the voltage value of analog voltage DI, the magnitude relationship with voltage signal Vout is reversed after the crossing time, and output signal Vout becomes lower than analog voltage DI. Therefore, output signal Vout is able to rise until it becomes higher than analog voltage DI, and reaches a voltage level that is almost the same as the peak value of analog voltage DI.
However, if analog voltage DI has a small peak value and the trace of the voltage value of output signal Vout does not cross the trace of the voltage value of analog voltage DI, for example, as shown by curve (Z) in FIG. 6, output signal Vout is still higher than analog voltage DI, but is unable to reach a voltage level that is almost the same as the peak value of analog voltage DI. If the time period during which output voltage Vout is higher than analog voltage DI (Tj in the figure) is long, the waveform of output signal Vout is unable to draw the correct envelope of the peak value since output signal Vout is not on almost the same voltage level as the peak value of analog voltage DI during that period, as shown by curve (Z) in FIG. 6.
As described above, since the amount of drop of output signal Vout per unit time is determined by the amount of sink constant current I2 generated by sink-side constant current circuit (124), if the amount of sink constant current I2 is increased, the amount of drop of output signal Vout per unit time can be increased. Therefore, even if analog voltage DI drops sharply, the output signal Vout is able to drop below analog voltage DI in a relatively short amount of time to match with the peak value. Sink constant current I2 flows constantly, however. The power consumption will be increased if the amount of sink constant current in constant flow is increased. Also, if the amount of rise or amount of drop of output signal Vout per unit time is increased, the flatness of the waveform of output signal Vout will deteriorate.
One aspect of the present invention is to solve the problem of the aforementioned conventional technology by providing a technology, such as a peak hold circuit, that can obtain and output peak value correctly to follow the variation in analog voltage.
In order to realized the aforementioned purpose, one aspect of the present invention provides a signal hold circuit having the following: a comparison circuit that compares an input signal with an output signal and outputs a comparison signal, a capacitor used for generating the aforementioned output signal, a first constant current circuit used for supplying a first current to the aforementioned capacitor, a second constant current circuit used for supplying a second current with opposite polarity to that of the first current to the aforementioned capacitor, a third constant current circuit used for supplying a third current with opposite polarity to that of the first current to the aforementioned capacitor, a first switch element that is electrically connected between the aforementioned capacitor and the first constant current circuit and is turned on corresponding to the aforementioned comparison signal, a rectifying element that is electrically connected between the aforementioned first switch element and the aforementioned capacitor, a second switch element that is connected between the aforementioned capacitor and the third constant current circuit, and a control circuit that uses the aforementioned comparison signal as its input and outputs a control signal for closing the second switch element when the comparison signal does not change during a prescribed amount of time.
In the signal hold circuit of one aspect of the present invention, it is preferred that the aforementioned input signal be an analog signal that varies periodically and the aforementioned prescribed amount of time be longer than one period of the aforementioned analog signal. Also, it is preferred that the aforementioned prescribed amount of time be shorter than two periods of the analog signal.
In the signal hold circuit of one aspect of the present invention, it is preferred that the aforementioned control circuit have a counter that is reset by a logical change in the aforementioned comparison signal and measures the aforementioned prescribed amount of time by counting a clock signal.
In addition, in the signal hold circuit of one aspect of the present invention, it is preferred that the aforementioned output signal be the peak holding signal of the aforementioned input signal.
The signal hold circuit of one aspect of the present invention has a control circuit that changes the amount of the current used to charge or discharge the capacitor when the polarity of the comparison signal does not change in a prescribed amount of time.
The polarity of the comparison signal corresponds to the magnitude relationship between the input and output signals. If the polarity of the comparison signal does not change in a prescribed amount of time, the output signal remains at a level that is either higher or lower than the input signal, and the magnitude relationship between the output and input signals does not change.
As described above, if the polarity of the comparison signal does not change in a prescribed amount of time, which is predetermined, the amount of the current for charging or discharging the capacitor will be changed by the control circuit to change the amount of variation in the output signal per unit time.
In particular, in the case of changing the output signal to follow the change in the input signal, for example, when the change in the output signal is unable to follow a sharp change in the input signal, the polarity of the comparison signal does not change over a long amount of time, and the magnitude relationship does not change, either.
When the amount of variation of the output signal per unit time is increased by using the control circuit to change the amount of current used to charge or discharge the capacitor if the polarity of the comparison signal does not change in a prescribed amount of time, the magnitude relationship will be reversed so that the output signal can be changed to follow the change in the input signal.
When the second switch element is turned on by the control circuit, in addition to the constant current flowing to the second constant current circuit that is connected in parallel with the third constant current circuit (auxiliary constant current circuit), the auxiliary constant current (the third current) flowing to the auxiliary constant current circuit also flows to the capacitor. Therefore, the amount of current used to charge or discharge the capacitor is changed.
A clock signal (reference clock signal) is input to the control circuit. The control circuit is constituted appropriately to count the number of reference clock pulses to measure a prescribed amount of time. In that case, the number of counted clock pulses is reset when the polarity of the comparison signal changes. Since the measured time is reset when the polarity of the comparison signal changes, measurement of a prescribed amount of time can always start from the point in time when the polarity of the comparison signal changes.